The industry’s most advanced process nodes do not support 3.3V signaling and 5V tolerance as required by the USB 2.0 specification. 3.3V signaling was originally defined in the USB 1.0 specification from 1994 and is required for backwards compatibility. Embedded USB2.0 (eUSB 2.0) is a new generation specification proposed by the USB Association that extends the USB 2.0 specification and uses 1.2V/1.0V as the interface operating voltage. The eUSB2 IP supports native mode and repeater mode, to make the application more flexible. The eUSB2 repeater converts between standard USB 2.0 and eUSB2 signaling levels, allowing legacy USB 2.0 devices to connect to a system-on-chip (SoC) with eUSB2 PHY.
Building on years of customer successes with our silicon-proven USB PHY product line , Innosilicon provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0 specifications. Innosilicon eUSB2 PHY IP has excellent combination of low area and low power in leading process technologies from 7nm and below.
Fully compliant with Embedded Universal Serial Bus 2.0 (eUSB) electrical specification.
Designed for advanced process nodes (7nm and below)
Minimizes effects due to variations in process, voltage, temperature, package, and board parasitics
Supports USB 2.0 480Mbps (High Speed), 12Mbps (Full Speed), and 1.5Mbps (Low Speed) data rates
Lowest power: Extended battery life in advanced mobile devices for eUSB2 chip-to-chip communication
Low power consumption
High speed hub use VLPI low latency
Simple integration process
Available options include
Test chips and test boards
FPGA integration support
Chip level integration
Databook and detailed physical implementation guides for the complete PHY
Library Exchange Format (LEF) file with pin size and locations
Gate-level netlist and Standard Delay Format (SDF) Timing file
Encrypted Verilog Models
Layout Versus Schematic (LVS) flattened netlist and report
Design Rule Check (DRC) report
GDSII database for foundry merge
Optional Test-chip and FPGA support
Optional backend integration