HBM2e/3 Solution

JESD235C 标准概述的第三代 HBM (HBM2e/3) 技术继承了具有 2n/4n 预取架构、内部组织、1024 位输入/输出、1.2 VI/O 和内核电压的物理 128 位 DDR 接口作为 以及原始技术中的所有关键部分。 与前代产品一样,HBM2e/3 在每个 KGSD 的基本逻辑芯片(2Hi、4Hi、8Hi、12Hi 堆栈)上支持两个、四个、八个或十二个 DRAM 设备。 HBM Gen 3 将堆栈内 DRAM 设备的容量扩展到 24GB,并将数据速率提高到每个引脚 7.2Gb/s。 此外,新技术带来了带宽最大化的重要改进。

INNO HBM2e/3 是 Innosilicon 广泛的前沿内存PHY和控制器controller IP 产品组合的一部分,其它还包括 GDDR6/6X 和 DDR5/LPDDR5。 Innosilicon 产品系列由具有丰富专业知识的经验丰富的团队开发,使客户能够获得最佳设计结果,同时加快上市时间。

The third-generation HBM (HBM2e/3) technology, outlined by the JESD235C standard, inherits physical 128-bit DDR interface with 2n/4n prefetch architecture, internal organization, 1024-bit input/output, 1.2 V I/O and core voltages as well as all the crucial parts in the original technology. Just like the predecessor, HBM2e/3 supports two, four, eight or twelve DRAM devices on a base logic die (2Hi, 4Hi, 8Hi, 12Hi stacks) per KGSD. HBM Gen 3 expands the capacity of DRAM devices within a stack to 24GB and increases the data rate by up to 7.2Gb/s per pin. In addition, the new technology brings an important improvement to bandwidth maximization.

The INNO HBM2e/3 is part of Innosilicon’s broad leading-edge memory IP portfolio that includes GDDR6/6X and DDR5/LPDDR5. Developed by the experienced team with great expertise, the Innosilicon product family enables customers to achieve the best design results while accelerating time to market.


  • Data rate up to 7.2Gbps with HBM3, up to 3.6Gbps with HBM2e

  • Supports 12-high DRAM stack with capacity up to 24GB per stack

  • Up to 920GB/s of data bandwidth for each cube with HBM3

  • Up to 460GB/s of data bandwidth for each cube with HBM2e

  • ECC and DBI/DM supported

  • Programmable 18mA driver with calibration

  • Multiple receivers for power and speed trade off

  • Balanced clock tree to reduce skew among bits

  • Various clock gating and low power modes

  • Measures taken to reduce simultaneous switching power/noise, for both DBI on and off

  • Self heating and aging effect carefully evaluated, IR/EM fixed to the best possible

  • Supports micro-bump and TSV package

  • Interposer routing straightly across Controller and DRAM with unified routing length for all bits

  • Interoperability test supporting any third-party DFI 4.0-compliant memory controller

  • IEEE1500 port supported for separate direct access to the memory stack and PHY


  • Substantially increases bandwidth available to computing devices

  • Fully pre-assemble design, drop-in hard macro to ease integration and speed time to market

  • Offers leading performance, power, and area per terabit

  • Extensive EDA tool support for various design automation flows

  • DFT functions to reduce test time and ensure high test coverage

  • Proven capabilities in PHY and silicon interposer design and integration

  • Optional PI/SI and thermal co-design service

  • Full support from IP delivery to production





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