The INNOSILICON USB 2.0 OTG PHY is fully compliant with UTMI+ level 3 Rev 1.0 specification. Offering excellent performance combined with a die size up to 30% less than competitor's solution, this PHY is the perfect companion to your design. The impressively small die size offers all functionality needed for a complete USB solution including HS, FS and LS support with OTG, as well as all required I/Os, primary and secondary ESD, self-calibrated DP/DM termination and an integrated PLL.
The UTMI+ interface can be pre-configured for either a 30MHz 16-bit, or 60Mhz 8-bit data interface.
If your solution requires more than one USB port, a further size efficiency can be achieved by choosing a multi-port solution. The INNOSILICON USB 2.0 PHY is available in 1, 2, 3 and 4-port configurations.
To support production test with high coverage, this PHY includes BIST, loop back, and boundary scan functionality.
All major processes fully covered, such as 110nm, 55nm to 28nm, 22nm, 14nm, 12nm, 8nm, 7nm, 6nm, 5nm.
USB 2.0 OTG spec compliant
8 bit or 16 bit UTMI+ interface compliant with UTMI+ specification level 3 Rev 1.
Battery charging support
HUB mode with 40 bit time round trip delay
Boundary Scan and Loop back BIST modes
Supports all USB 2.0 specified test modes
Built-in I/O complete with primary and secondary ESD structures
On-die self-calibrated HS/FS/LS termination
12/24MHz crystal oscillator with Integrated phase-locked loop (PLL) oscillator
Low power operation, 80mW analog power Max for 2 ports High speed transmission
Low power consumption
High speed hub use VLPI low latency
Simple integration process
Available options include
Test chips and test boards
FPGA integration support
Chip level integration